1. Field of the Invention
The present invention relates to a layout structure of a semiconductor memory device and more particularly to a layout structure and method of a column path of a semiconductor memory device for accomplishing high integration on a minimized layout area of column pass transistors connected to memory cells, thereby effectively constructing a layout structure of the column pass transistors.
2. Description of the Prior Art
Since the metal oxide semiconductor (MOS) transistor was invented to replace a bipolar transistor, semiconductor memory device technology has made amazing progress all over the world very recently.
Such noteworthy progress in the semiconductor memory device has also triggered another advance in the high integration technology by which a great number of elements are integrated on a single wafer. Such a technological improvement in a highly integrated device has been attributed to a revolutionary technology called xe2x80x9cvery large scale integration (VLSI).xe2x80x9d The VLSI revolutionary technology takes a lead in the field of micro-electronics represented by ultra-fine process techniques, sub-micron element techniques, circuit designing techniques in dynamic random access memory (hereinafter referred to as DRAM) and static random access memory (hereinafter referred to as SRAM).
Among these advances, the technical progress in the ultra-fine process techniques and the sub-micron element techniques leads to high integration and large capacity of a semiconductor memory device characterized by memory cells of a smaller size.
However, the area occupied with the interface or peripheral circuits of the memory cells becomes relatively large in contrast to miniaturization of the memory cells, so that this interface or peripheral circuit area becomes one of the important factors in determining the size of a chip. This remains as a problem to all semiconductor manufacturers that develop a miniature chip under high density. In other words, development of a miniaturized chip layout structure becomes an important factor in miniaturizing various electronic products including the semiconductor memory device, thereby to improve the competitiveness of those products.
Among them, the area of the column path to provide a read/write data path of a memory cell is an important factor in determining the size of a chip, so that it is necessary to make a layout structure wherein the area of the column path is a minimum allowable in accordance with the design rule of the chip.
In general, the layout structure of the cell interface has been determined according to the shape of the memory cell, which heretofore as been made with a long Y-axis. Due to limitations of the design rule, linear column pass transistors, e.g. NMOS or PMOS transistors, have been arranged in parallel to the bit line pairs BL/BLB. However, if the X-axis of a memory cell gets too short, there may be a reduction in the area of the column pass transistors to be arranged in the bit line pairs.
Moreover, there may be a limitation in the conventional layout structure due to the reduction to be made in the tiny area for column pass transistors. In other words, scaling down of each memory cell can lead to a reduction in the area to be occupied by all memory cells, so that it becomes impractical to use the conventional layout structure of the column pass transistors. Thus, in order to accommodate smaller memory cells, the layout structure of a cell interface, for instance, the column pass transistors, should be improved as the scaling down of the chip continues.
Therefore, the conventional layout structure of the column pass transistors may no longer be properly applied to the miniature memory cells in the near future. Thus, it is required to develop a layout structure of the column pass transistors that is different from the conventional one since it is easily predicted that memory cells will be smaller and smaller.
However, if a proper layout structure cannot be made for the column pass transistors, all the efforts focused on miniaturization of a memory cell will be in vain in spite of a success in making a smaller memory cell. In other words, if a more efficient layout structure of column pass transistors is developed along with a progress in miniaturization of a memory cell, it will make a contribution to miniaturization of a chip. If a newly developed layout structure of the column pass transistors can further reduce the area for the column pass transistors, it will be advantageous in miniaturization of a semiconductor chip and enhancement of all manufacturers"" efforts to reduce the size of a chip.
Besides, there has been another problem in the conventional column path layout structure in that the bit lines and the section data lines commonly combining inputs and outputs are made of different materials. For example, the bit lines typically have been made of a first metal layer and the section data lines have been made of a different metal, e.g., tungsten. Thus, undesirable loading of the inputs and outputs increases.
The present invention to solves the aforementioned problems and it is an object of the present invention to provide a layout structure of column pass transistors which can be efficiently arranged in the area of memory cells which may be manufactured much smaller than the conventional layout structure.
It is another object of the present invention to provide a column path layout structure of a semiconductor memory device not only to reduce the size of memory cells, but also effectively and efficiently to make a contribution to miniaturization of chips for a semiconductor memory device.
It is still another object of the present invention to provide a column path layout structure of a semiconductor memory device and a method related thereto that can solve the aforementioned problem of increased loads on bit lines and section data lines made of different materials.
In order to accomplish the aforementioned objects of the present invention, there is provided a column path layout structure of a semiconductor memory device wherein the longitudinal direction of active regions of the same conductivity type of first and second transistors respectively connected to bit lines further connected with a plurality of memory cells is approximately perpendicular to that of the bit line pairs.